PUBLICATIONS

 This thesis presents the analysis and design of a minimum-loss discontinuous pulse width modulation (MLDPWM) scheme for a single-inverter dual-parallel (SIDP) interior permanent magnet synchronous motor (IPMSM) drive system. The single objective of this thesis is to minimize the inverter switching loss of the SIDP IPMSM drive across its full load-imbalance range. The speed synchronization between the two motors is not a contribution of this work; it is already secured by the active damping controller and is treated throughout as a fixed operating constraint that the modulation scheme must preserve. A single three-phase two-level voltage source inverter supplies two IPMSMs whose stator terminals are connected in parallel, with one motor regulated by a cascaded vector controller and the other stabilized by an active damping controller. Because the inverter current is the vector sum of the two stator currents, its phase relative to the inverter voltage shifts with the load imbalance between the two motors. This shift causes conventional voltage-phase discontinuous pulse width modulation (DPWM) and conventional current-phase DPWM to lose their switching-loss-minimization property in opposite operating regions. The proposed MLDPWM combines a current-phase clamping rule with a voltage phase based rail-clamping rule and selects between them according to the load imbalance ratio, with a hysteresis band to suppress chattering. The zero-sequence offset voltage is synthesized in carrier-based form so that the scheme is implementable on a standard digital signal processor without modifying the existing current loop. The inverter switching loss is modeled using a linear energy-per-event formulation referenced to representative IGBT datasheet parameters. The MLDPWM strategy reduces inverter loss by aligning the clamping interval with the phase carrying the largest instantaneous resultant current whenever current peak detection remains reliable. Since the energy dissipated during a switching event is proportional to the current at the switching instant, suppressing switching transitions in the highest current phase reduces the dominant switching loss component. The remaining switching transitions occur in phases carrying lower instantaneous currents, which further supports the minimum loss objective. The proposed method is verified through time-domain PSIM simulation under balanced, mild-imbalance, and severe-imbalance operating conditions and is compared against space vector pulse width modulation (SVPWM) and conventional DPWM. The simulation results indicate that the proposed scheme achieves the lowest total inverter loss across all tested operating conditions. The current quality and the primary-secondary speed synchronization are preserved within the design bounds.