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This article presents a reduction method of circulating current in parallel three-level inverters using modified discontinuous pulse-width modulation (DPWM) based on an interleaving scheme. The harmonics and current ripple are the same as that of a single inverter with the same current capacity as the parallel system with DPWM. An interleaved DPWM improves the output current quality. However, a circulating current is generated by the

asynchronous phase carriers. The circulating current limits the power rating. To alleviate these problems, the proposed method reduces the high-frequency circulating current with switching frequency by 79% even at a high modulation index. The switching sequence and high-frequency circulating current are analyzed to prove the performance of the proposed method. The effectiveness and reliability of the proposed reduction method are compared to the conventional SVM. The validity of the proposed method is verified through simulations and experimental results.