PUBLICATIONS

This thesis presents a DC-link ripple current minimization method to extend the capacitor lifetime in three-level voltage source inverters (3L-VSIs). A DC-link ripple current is defined as the current that flows through the DC-link capacitors. When the space vector pulse width modulation (SVPWM) is adopted as a modulation method of the 3L-VSIs, a large DC-link ripple current is produced when the small vectors are applied. The produced large DC-link ripple current generates high heat losses in the DC-link capacitors, which shortens their lifetime and ultimately reduces the reliability of the 3L-VSIs. To mitigate the problem caused by the large DC-link ripple current, the proposed method substitutes the small vectors of SVPWM with large vectors. As the large vectors induce zero DC-link ripple currents, the minimized DC-link ripple currents and resulting extended lifetime of DC-link capacitors can be attained with the proposed method. In addition, the proposed method guarantees the neutral point voltage balancing, which is essential in the operation of 3L-VSIs. The performance and feasibility of the proposed method are demonstrated by simulation and experimental results.